Fedora21有没有thunderbird?

感觉这个邮件客户端比现在内置的claws mail好用。
能移植一下吗?
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loongnix

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已经编译过了Fedora22内置的thunderbird-31.6.0-1.fc22.src.rpm。在龙芯上运行功能正常。
 
原始代码需要针对mips64el平台进行以下的修改才能编译通过:
 
diff --git a/comm-esr31/mozilla/ipc/chromium/src/base/atomicops_internals_mips_gcc.h b/comm-esr31/mozilla/ipc/chromium/src/base/atomicops_internals_mips_gcc.h
index e8a1c76..80f5feb 100644
--- a/comm-esr31/mozilla/ipc/chromium/src/base/atomicops_internals_mips_gcc.h
+++ b/comm-esr31/mozilla/ipc/chromium/src/base/atomicops_internals_mips_gcc.h
@@ -1,4 +1,4 @@
-// Copyright 2010 the V8 project authors. All rights reserved.
+// Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
@@ -25,13 +25,13 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-// This file is an internal atomic implementation, use atomicops.h instead.
+// This file is an internal atomic implementation, use base/atomicops.h instead.
+//
+// LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears.

#ifndef GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_MIPS_GCC_H_
#define GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_MIPS_GCC_H_

-#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
-
namespace base {
namespace subtle {

@@ -61,7 +61,7 @@ inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
"2:\n"
".set pop\n"
: "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
- : "Ir" (old_value), "r" (new_value), "m" (*ptr)
+ : "r" (old_value), "r" (new_value), "m" (*ptr)
: "memory");
return prev;
}
@@ -74,7 +74,7 @@ inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
__asm__ __volatile__(".set push\n"
".set noreorder\n"
"1:\n"
- "ll %1, %2\n" // old = *ptr
+ "ll %1, %4\n" // old = *ptr
"move %0, %3\n" // temp = new_value
"sc %0, %2\n" // *ptr = temp (with atomic check)
"beqz %0, 1b\n" // start again on atomic error
@@ -96,7 +96,7 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
__asm__ __volatile__(".set push\n"
".set noreorder\n"
"1:\n"
- "ll %0, %2\n" // temp = *ptr
+ "ll %0, %4\n" // temp = *ptr
"addu %1, %0, %3\n" // temp2 = temp + increment
"sc %1, %2\n" // *ptr = temp2 (with atomic check)
"beqz %1, 1b\n" // start again on atomic error
@@ -111,9 +111,9 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,

inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
Atomic32 increment) {
- ATOMICOPS_COMPILER_BARRIER();
+ MemoryBarrier();
Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
- ATOMICOPS_COMPILER_BARRIER();
+ MemoryBarrier();
return res;
}

@@ -126,19 +126,16 @@ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
- ATOMICOPS_COMPILER_BARRIER();
Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
- ATOMICOPS_COMPILER_BARRIER();
+ MemoryBarrier();
return res;
}

inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
- ATOMICOPS_COMPILER_BARRIER();
- Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
- ATOMICOPS_COMPILER_BARRIER();
- return res;
+ MemoryBarrier();
+ return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
}

inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
@@ -174,9 +171,133 @@ inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
return *ptr;
}

-} // namespace subtle
-} // namespace base
+#if defined(__LP64__)
+// 64-bit versions of the atomic ops.
+
+inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
+ Atomic64 old_value,
+ Atomic64 new_value) {
+ Atomic64 prev, tmp;
+ __asm__ __volatile__(".set push\n"
+ ".set noreorder\n"
+ "1:\n"
+ "lld %0, %5\n" // prev = *ptr
+ "bne %0, %3, 2f\n" // if (prev != old_value) goto 2
+ "move %2, %4\n" // tmp = new_value
+ "scd %2, %1\n" // *ptr = tmp (with atomic check)
+ "beqz %2, 1b\n" // start again on atomic error
+ "nop\n" // delay slot nop
+ "2:\n"
+ ".set pop\n"
+ : "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
+ : "r" (old_value), "r" (new_value), "m" (*ptr)
+ : "memory");
+ return prev;
+}
+
+// Atomically store new_value into *ptr, returning the previous value held in
+// *ptr. This routine implies no memory barriers.
+inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
+ Atomic64 new_value) {
+ Atomic64 temp, old;
+ __asm__ __volatile__(".set push\n"
+ ".set noreorder\n"
+ "1:\n"
+ "lld %1, %4\n" // old = *ptr
+ "move %0, %3\n" // temp = new_value
+ "scd %0, %2\n" // *ptr = temp (with atomic check)
+ "beqz %0, 1b\n" // start again on atomic error
+ "nop\n" // delay slot nop
+ ".set pop\n"
+ : "=&r" (temp), "=&r" (old), "=m" (*ptr)
+ : "r" (new_value), "m" (*ptr)
+ : "memory");
+
+ return old;
+}
+
+// Atomically increment *ptr by "increment". Returns the new value of
+// *ptr with the increment applied. This routine implies no memory barriers.
+inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
+ Atomic64 increment) {
+ Atomic64 temp, temp2;
+
+ __asm__ __volatile__(".set push\n"
+ ".set noreorder\n"
+ "1:\n"
+ "lld %0, %4\n" // temp = *ptr
+ "daddu %1, %0, %3\n" // temp2 = temp + increment
+ "scd %1, %2\n" // *ptr = temp2 (with atomic check)
+ "beqz %1, 1b\n" // start again on atomic error
+ "daddu %1, %0, %3\n" // temp2 = temp + increment
+ ".set pop\n"
+ : "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
+ : "Ir" (increment), "m" (*ptr)
+ : "memory");
+ // temp2 now holds the final value.
+ return temp2;
+}
+
+inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
+ Atomic64 increment) {
+ MemoryBarrier();
+ Atomic64 res = NoBarrier_AtomicIncrement(ptr, increment);
+ MemoryBarrier();
+ return res;
+}
+
+// "Acquire" operations
+// ensure that no later memory access can be reordered ahead of the operation.
+// "Release" operations ensure that no previous memory access can be reordered
+// after the operation. "Barrier" operations have both "Acquire" and "Release"
+// semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
+// access.
+inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
+ Atomic64 old_value,
+ Atomic64 new_value) {
+ Atomic64 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
+ MemoryBarrier();
+ return res;
+}
+
+inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
+ Atomic64 old_value,
+ Atomic64 new_value) {
+ MemoryBarrier();
+ return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
+}
+
+inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
+ *ptr = value;
+}
+
+inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
+ *ptr = value;
+ MemoryBarrier();
+}
+
+inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
+ MemoryBarrier();
+ *ptr = value;
+}
+
+inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
+ return *ptr;
+}
+
+inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
+ Atomic64 value = *ptr;
+ MemoryBarrier();
+ return value;
+}
+
+inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
+ MemoryBarrier();
+ return *ptr;
+}
+#endif

-#undef ATOMICOPS_COMPILER_BARRIER
+} // namespace base::subtle
+} // namespace base

#endif // GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_MIPS_GCC_H_
diff --git a/comm-esr31/mozilla/ipc/chromium/src/base/port.h b/comm-esr31/mozilla/ipc/chromium/src/base/port.h
index 573f5f0..f30a74c 100644
--- a/comm-esr31/mozilla/ipc/chromium/src/base/port.h
+++ b/comm-esr31/mozilla/ipc/chromium/src/base/port.h
@@ -6,7 +6,7 @@
#define BASE_PORT_H_

#include <stdarg.h>
-#include "build/build_config.h"
+#include "../build/build_config.h"

#ifdef COMPILER_MSVC
#define GG_LONGLONG(x) x##I64
diff --git a/comm-esr31/mozilla/ipc/chromium/src/build/build_config.h b/comm-esr31/mozilla/ipc/chromium/src/build/build_config.h
index e3f4189..2648b1a 100644
--- a/comm-esr31/mozilla/ipc/chromium/src/build/build_config.h
+++ b/comm-esr31/mozilla/ipc/chromium/src/build/build_config.h
@@ -87,6 +87,9 @@
#elif defined(__sparc__)
#define ARCH_CPU_SPARC 1
#define ARCH_CPU_32_BITS 1
+#elif defined(__mips64) && defined(__LP64__)
+#define ARCH_CPU_MIPS 1
+#define ARCH_CPU_64_BITS 1
#elif defined(__mips__)
#define ARCH_CPU_MIPS 1
#define ARCH_CPU_32_BITS 1
@@ -106,7 +109,8 @@
#define ARCH_CPU_ALPHA 1
#define ARCH_CPU_64_BITS 1
#elif defined(__aarch64__)
-#define ARCH_CPU_AARCH64 1
+#define ARCH_CPU_ARM_FAMILY 1
+#define ARCH_CPU_ARM64 1
#define ARCH_CPU_64_BITS 1
#else
#error Please add support for your architecture in build/build_config.h
@@ -120,3 +124,4 @@
#endif

#endif // BUILD_BUILD_CONFIG_H_
+
diff --git a/comm-esr31/mozilla/media/libyuv/include/libyuv/row.h b/comm-esr31/mozilla/media/libyuv/include/libyuv/row.h
index 3e86f28..2436851 100644
--- a/comm-esr31/mozilla/media/libyuv/include/libyuv/row.h
+++ b/comm-esr31/mozilla/media/libyuv/include/libyuv/row.h
@@ -38,7 +38,8 @@ extern "C" {
var = 0

#if defined(__pnacl__) || defined(__CLR_VER) || defined(COVERAGE_ENABLED) || \
- defined(TARGET_IPHONE_SIMULATOR)
+ defined(TARGET_IPHONE_SIMULATOR) || \
+ (defined(_MSC_VER) && defined(__clang__))
#define LIBYUV_DISABLE_X86
#endif
// True if compiling for SSSE3 as a requirement.
@@ -329,7 +330,7 @@ extern "C" {
#endif

// The following are available on Mips platforms:
-#if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__)
+#if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__) && (_MIPS_SIM == _ABIO32)
#define HAS_COPYROW_MIPS
#if defined(__mips_dsp) && (__mips_dsp_rev >= 2)
#define HAS_I422TOABGRROW_MIPS_DSPR2
@@ -341,6 +342,10 @@ extern "C" {
#define HAS_SPLITUVROW_MIPS_DSPR2
#endif
#endif
+#if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__) && \
+ defined(_MIPS_ARCH_LOONGSON3A)
+#define HAS_YUY2TOYROW_MMI
+#endif

#if defined(_MSC_VER) && !defined(__CLR_VER)
#define SIMD_ALIGNED(var) __declspec(align(16)) var
@@ -1383,6 +1388,9 @@ void YUY2ToUV422Row_NEON(const uint8* src_yuy2,
void YUY2ToYRow_C(const uint8* src_yuy2, uint8* dst_y, int pix);
void YUY2ToUVRow_C(const uint8* src_yuy2, int stride_yuy2,
uint8* dst_u, uint8* dst_v, int pix);
+void YUY2ToYRow_MMI(const uint8* src_yuy2, uint8* dst_y, int pix);
+void YUY2ToUVRow_MMI(const uint8* src_yuy2, int stride_yuy2,
+ uint8* dst_u, uint8* dst_v, int pix);
void YUY2ToUV422Row_C(const uint8* src_yuy2,
uint8* dst_u, uint8* dst_v, int pix);
void YUY2ToYRow_Any_AVX2(const uint8* src_yuy2, uint8* dst_y, int pix);
diff --git a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_asm_mips64.S b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_asm_mips64.S
index ed897f1..eef34de 100644
--- a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_asm_mips64.S
+++ b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_asm_mips64.S
@@ -51,15 +51,15 @@ NESTED(_NS_InvokeByIndex, FRAMESZ, ra)

# assume full size of 16 bytes per param to be safe
sll v0, 4 # 16 bytes * num params
- subu sp, sp, v0 # make room
+ PTR_SUBU sp, sp, v0 # make room
move a0, sp # a0 - param stack address

# create temporary stack space to write int and fp regs
- subu sp, 64 # 64 = 8 regs of 8 bytes
+ PTR_SUBU sp, 64 # 64 = 8 regs of 8 bytes
move a3, sp

# save the old sp and save the arg stack
- subu sp, sp, 16
+ PTR_SUBU sp, sp, 16
REG_S t0, 0(sp)
REG_S a0, 8(sp)

@@ -78,12 +78,12 @@ NESTED(_NS_InvokeByIndex, FRAMESZ, ra)

# calculate the function we need to jump to,
# which must then be saved in t9
- lw t9, 0(a0)
- addu t9, t9, t1
- lw t9, (t9)
+ PTR_L t9, 0(a0)
+ PTR_ADDU t9, t9, t1
+ PTR_L t9, (t9)

# get register save area from invoke_copy_to_stack
- subu t1, t3, 64
+ PTR_SUBU t1, t3, 64

# a1..a7 and f13..f19 should now be set to what
# invoke_copy_to_stack told us. skip a0 and f12
diff --git a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_mips64.cpp b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_mips64.cpp
index 08b4616..e5876e2 100644
--- a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_mips64.cpp
+++ b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcinvoke_mips64.cpp
@@ -7,8 +7,8 @@

#include "xptcprivate.h"

-#if (_MIPS_SIM != _ABIN32)
-#error "This code is for MIPS N32 only"
+#if (_MIPS_SIM != _ABIN32) && (_MIPS_SIM != _ABI64)
+#error "This code is for MIPS n32/n64 only"
#endif

extern "C" uint32_t
@@ -77,7 +77,9 @@ invoke_copy_to_stack(uint64_t* d, uint32_t paramCount,
break;
case nsXPTType::T_U32:
if (i < N_ARG_REGS)
- regs[i] = s->val.u32;
+ // 32-bit values need to be sign-extended
+ // in register, so use the signed value.
+ regs[i] = s->val.i32;
else
*d++ = s->val.u32;
break;
@@ -138,3 +140,4 @@ NS_InvokeByIndex(nsISupports* that, uint32_t methodIndex,
{
return _NS_InvokeByIndex(that, methodIndex, paramCount, params);
}
+
diff --git a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_asm_mips64.S b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_asm_mips64.S
index b7a0c72..11d8515 100644
--- a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_asm_mips64.S
+++ b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_asm_mips64.S
@@ -88,15 +88,15 @@ sharedstub:
# a2 is stack address where extra function params
# are stored that do not fit in registers
move a2, sp
- addi a2, FRAMESZ
+ PTR_ADDI a2, FRAMESZ

# a3 is stack address of a1..a7
move a3, sp
- addi a3, A1OFF
+ PTR_ADDI a3, A1OFF

# a4 is stack address of f13..f19
move a4, sp
- addi a4, F13OFF
+ PTR_ADDI a4, F13OFF

# PrepareAndDispatch(that, methodIndex, args, gprArgs, fpArgs)
# a0 a1 a2 a3 a4
diff --git a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_mips64.cpp b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_mips64.cpp
index 8797a56..a4b5539 100644
--- a/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_mips64.cpp
+++ b/comm-esr31/mozilla/xpcom/reflect/xptcall/src/md/unix/xptcstubs_mips64.cpp
@@ -6,12 +6,12 @@
#include "xptcprivate.h"
#include "xptiprivate.h"

-#if (_MIPS_SIM != _ABIN32)
-#error "This code is for MIPS N32 only"
+#if (_MIPS_SIM != _ABIN32) && (_MIPS_SIM != _ABI64)
+#error "This code is for MIPS n32/n64 only"
#endif

/*
- * This is for MIPS N32 ABI
+ * This is for MIPS n32/n64 ABI
*
* When we're called, the "gp" registers are stored in gprData and
* the "fp" registers are stored in fprData. There are 8 regs
--
2.1.0

loongnix

赞同来自:

thunderbird是firefox的一个项目,应该是目前最好用的Linux邮件客户端。
虽然现在大量使用Web Mail,但是本地邮件客户端还是有很多人在用,毕竟有操作方便、不上网也能查邮件的优点。
现在已经开始在编译thunderbird了,下一版本就内置了。

loongnix

赞同来自:

下一版Fedora21将集成这个thunderbird。

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