CPU

龙芯买了 mips64 r5授权

小道消息:如题,求证
  Release 5 ("R5") of the MIPS base architecture incorporates important functionality including virtualization and SIMD (Single Instruction Multiple Data) modules.

Highlights

Major release of the MIPS architecture-based on years of development-includes significant functionality for next-generation MIPS-Based™ products
MIPS SIMD architecture (MSA) module provides more computational capability for a wide range of applications
Scalable Virtualization (VZ) module provides secure hardware virtualization across a range of applications from tiny microcontrollers to high-end enterprise
Enhanced Virtual Addressing (EVA) technology extends available memory space for large modern workloads
Popular multi-threading and DSP extensions are now integrated as modules within the base MIPS architecture


https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64
 
MIPS32/MIPS64[edit]

When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Up to MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem,[citation needed] and the architecture definition was changed to define a 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999.[13] MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V.[13] NEC, Toshiba and SiByte (later acquired by Broadcom) each obtained licenses for MIPS64 as soon as it was announced. Philips, LSI Logic, IDT, Raza Microelectronics, Inc., Cavium, Loongson Technology and Ingenic Semiconductor have since joined them.

MIPS32/MIPS64 Release 1[edit]

The first release of MIPS32, based on MIPS II, added conditional moves, prefetch instructions, and other features from the R4000 and R5000 families of 64-bit processors.[13] The first release of MIPS64 adds a MIPS32 mode to run 32-bit code.[13] The MUL and MADD (multiply-add) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were cache control instructions.[13]

MIPS32/MIPS64 Release 2[edit]
MIPS32/MIPS64 Release 3[edit]
MIPS32/MIPS64 Release 5[edit]

Announced on December 6, 2012.[14] Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures.[15]

MIPS32/MIPS64 Release 6[edit]

MIPS32/MIPS64 Release 6 in 2014 added[16] the following:

a new family of branches with no delay slot:

unconditional branches (BC) & branch-and-link (BALC) with a 26-bit offset,
conditional branch on zero/non-zero with a 21-bit offset,
full set of signed & unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
full set of branch-and-link which compare a register against zero (e.g. BGTZALC).

index jump instructions with no delay slot designed to support large absolute addresses.
instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
bit-reversal & byte-alignment instructions (previously only available with the DSP extension).
multiply & divide instructions redefined so that they use a single register for their result).
instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.

Removed infrequently used instructions:

some conditional moves
branch likely instructions (deprecated in previous releases).
integer overflow trapping instructions with 16-bit immediate
integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
unaligned load instructions (LWL & LWR), (requiring that most ordinary loads & stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))

Reorganized the instruction encoding, freeing space for future expansions.
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jiangtao9999

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mips 的指令集太碎了。
不过虚拟机和simd又都必须有。
不知道龙心打算怎么用,别学龙心2f时代直接更新到r2放弃旧的支持。
 
话说我希望的是保持r2状态仅增加新的功能指令集。这样强制软件还用r2状态。但是软件可以显式的使用新扩展。
至于simd,我倒是觉得应该有自己的方案了。
可以用内置显卡模块,按需切换成fpu/simd/显卡模式。
而且还是多个这种模块,可以按需切换的。
呵呵

water

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water

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3a2000 
基于MIPS32/64R3(共216条基础+311条DSP指令)
,通过MIPS架构的UD1进行扩展
·基础扩展LoongEXT(共148条指令)

    ·如定应乘除、多核稀步、128位访存。CAM
·虚拟机扩展LoongVM(共5条指令)
     .支持云计算需要的多操作养统快速韧换
·二进制翻译扩展LongBT(共215条指令)、
·     支持X86/ARM到LoonglSA的高效翻译、

向量指令扩展LoongSIMD(共1014条指令)。
       128位(32位模式》及256位(64位模式)向量指令
 
最新的是
基于MIPS32/64R5(共279条基础+159条DSP指令+900条SMID+37条加解密)
·基础扩展LoongEXT(共186条指令)
    ·如定应乘除、多核稀步、128位访存。CAM

·二进制翻译扩展LongBT(共157条指令)、
·     支持X86/ARM到LoonglSA的高效翻译、

向量指令扩展LoongSIMD(共477条指令)。
       128位(32位模式》及256位(64位模式)向量指令
 
好了 ,问题来了那些少掉了指令是被废弃了 还是 ????
一个乱字了得。

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