CPU

20180904的PMON根据硬件3a2000+rs780配置编译烧录到我们的板子挂机

PMON2000 MIPS Initializing. Standby...

0xbfe00190  : 000085ef00000000
CPU CLK SEL : 0000000f
MEM CLK SEL : 0000000f
Soft CLK SEL adjust begin
CORE & NODE:00010c85
MEM        :040c007b
fdcoefficient  :00000000
HT         :01400140

MC RESET
Fix L1xbar illegal access at NODE 0
Fix L2xbar in NODE 0
32 bit PCI space translate to 64 bit HT space
Waiting HyperTransport bus to be up.00112020>
00112020
HT RX DMA address ENABLE
HT RX DMA address ENABLE done 1
HT RX DMA address ENABLE done 2
Set HT Memory space all post
Setting HyperTransport Controller to be 8-bit width
00112020
Setting HyperTransport Controller to be 800Mhz
02258523
SET HT as HOST
2001000820010008
Setting HyperTransport Southbridge to be 8-bit width
00110020
Setting HyperTransport Southbridge to be 800M
Setting Watch Dog to make a WARM RESET
Watch dog Enable

Watch dog decode enable
00000000
Watch dog control value
00000000
00000000
Set Watch dog control value
Waiting HyperTransport bus to be down.>
00112010
Waiting HyperTransport bus to be up.===========>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
00112020
Setting HyperTransport Southbridge back to be 8-bit width and 200Mhz for next RESET

Checking HyperTransport bus CRC error bit.
Checking HyperTransport SouthBridge CRC error bit.
Done
Read HT Channel priority
00904321
Jump to 9fc

Start Init Memory, wait a while......
NODE 0 MEMORY CONFIG BEGIN

Open SMBUS controller

Probing DDR MC1 SLOT:
Probe MC1 slot 0.
Probe MC1 slot 1.
NO DIMM in this slot.

Probing DDR MC0 SLOT:
Probe MC0 slot 0.
Probe MC0 slot 1.
NO DIMM in this slot.


s1 = 0xc0e31000__c0e31000

new s1 = 0xc1e30800__c1e30800
Disable cpu buffered read
Disable read buffer

Enable register space of MEMORY
run to wait dram init ok!3

Disable register space of MEMORY

Disable register space of MEMORY done.
Start Hard Leveling...

Enable register space of MEMORY

write leveling begin

all dll_wrdqs set 0

set leveling mode to be WRITE LEVELING

write leveling ready
000000010000000200000003000000040000000500000006000000070000000800000008
write leveling finish and gate leveling begin

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

MC0 Config DONE

Enable register space of MEMORY
run to wait dram init ok!3

Disable register space of MEMORY

Disable register space of MEMORY done.
Start Hard Leveling...

Enable register space of MEMORY

write leveling begin

all dll_wrdqs set 0

set leveling mode to be WRITE LEVELING

write leveling ready
000000010000000200000003000000040000000500000006000000070000000800000008
write leveling finish and gate leveling begin

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

PREAMBLE CHECK!!

The preamble check failed @00000055

PREAMBLE CHECK!!

The preamble check success

MC1 Config DONE
!!!MEM is at NO_INTERLEAVE mode. If this is not the expected setting,
please check whether the two MC_MEMSIZE is equal
DDR space open : 0x00000000 - 0x0FFFFFFF
PCI space open: 0x80000000 - 0x8FFFFFFF
MC0 space open : 0x80000000 - 0xFFFFFFFF
MC1 space open : 0x100000000 - 0x1FFFFFFFF
MC0 space open : 0x200000000 - 0x27FFFFFFF
DDR space open : 0x080000000 - 0x27FFFFFFF
Full PCI space opened as cpu.

msize = 0x00000010
Init Memory done.
The uncache data is:
00000000:  5555555555555555
00000008:  aaaaaaaaaaaaaaaa
00000010:  3333333333333333
00000018:  cccccccccccccccc
00000020:  7777777777777777
00000028:  8888888888888888
00000030:  1111111111111111
00000038:  eeeeeeeeeeeeeeee
The cached  data is:
00000000:  5555555555555555
00000008:  aaaaaaaaaaaaaaaa
00000010:  3333333333333333
00000018:  cccccccccccccccc
00000020:  7777777777777777
00000028:  8888888888888888
00000030:  1111111111111111
00000038:  eeeeeeeeeeeeeeee

 enable rs780 dev8...

 Enabled GPPSB success...

 sb700 lpc init...

 set boottimerdisable

 enable lpc controller

 enable port 80 LPC decode

 Decode port 0x3f8-0x3ff

 Decode port 0x60-0x66

 SuperIO RTC

======X1 core0 map windows:
900000003ff02000: 0000000018000000
900000003ff02008: 00000e0000000000
900000003ff02010: 0000000000000000
900000003ff02018: 0000000040000000
900000003ff02020: 000000001e000000
900000003ff02028: 00000c0000000000
900000003ff02030: 0000200000000000
900000003ff02038: 0000100000000000
900000003ff02040: fffffffffc000000
900000003ff02048: ffffff0000000000
900000003ff02050: 0000000000000000
900000003ff02058: ffffffffc0000000
900000003ff02060: ffffffffff000000
900000003ff02068: 00000c0000000000
900000003ff02070: 0000200000000000
900000003ff02078: 0000300000000000
900000003ff02080: 00000efdfc0000f7
900000003ff02088: 00000e00000000f7
900000003ff02090: 0000000000000000
900000003ff02098: 00000e00400000f7
900000003ff020a0: 00000e00000000f7
900000003ff020a8: 00000c00000000f7
900000003ff020b0: 00002000000000f7
900000003ff020b8: 00001000000000f7

======X1 ht map windows:
900000003ff02700: 0000000000000000
900000003ff02708: 0000000000000000
900000003ff02710: 0000000000000000
900000003ff02718: 0000000000000000
900000003ff02720: 0000000000000000
900000003ff02728: 00000c0000000000
900000003ff02730: 0000200000000000
900000003ff02738: 0000100000000000
900000003ff02740: 0000000000000000
900000003ff02748: 0000000000000000
900000003ff02750: 0000000000000000
900000003ff02758: 0000000000000000
900000003ff02760: 0000000000000000
900000003ff02768: 00000c0000000000
900000003ff02770: 0000200000000000
900000003ff02778: 0000300000000000
900000003ff02780: 0000000000000000
900000003ff02788: 0000000000000000
900000003ff02790: 0000000000000000
900000003ff02798: 0000000000000000
900000003ff027a0: 0000000000000000
900000003ff027a8: 00000c00000000f7
900000003ff027b0: 00002000000000f7
900000003ff027b8: 00001000000000f7

======X2 cpu map windows:
900000003ff00000: 000000001fc00000
900000003ff00008: 0000000010000000
900000003ff00010: 0000000000000000
900000003ff00018: 0000000000000000
900000003ff00020: 0000000080000000
900000003ff00028: 0000000100000000
900000003ff00030: 0000000200000000
900000003ff00038: 0000000000000000
900000003ff00040: fffffffffff00000
900000003ff00048: fffffffff0000000
900000003ff00050: fffffffff0000000
900000003ff00058: 0000000000000000
900000003ff00060: ffffffff80000000
900000003ff00068: ffffffff00000000
900000003ff00070: ffffffff80000000
900000003ff00078: 0000000000000000
900000003ff00080: 000000001fc000f2
900000003ff00088: 0000000010000082
900000003ff00090: 00000000000000f0
900000003ff00098: 0000000000000000
900000003ff000a0: 00000000000000f0
900000003ff000a8: 00000000000000f1
900000003ff000b0: 00000000800000f0
900000003ff000b8: 0000000000000000

======X2 pci map windows:
900000003ff00100: 0000000080000000
900000003ff00108: 0000000000000000
900000003ff00110: 0000000080000000
900000003ff00118: 0000000080000000
900000003ff00120: 0000000080000000
900000003ff00128: 0000000100000000
900000003ff00130: 0000000200000000
900000003ff00138: 0000000000000000
900000003ff00140: ffffffff80000000
900000003ff00148: 0000000000000000
900000003ff00150: fffffffff0000000
900000003ff00158: 0000000000000000
900000003ff00160: ffffffff80000000
900000003ff00168: ffffffff00000000
900000003ff00170: ffffffff80000000
900000003ff00178: 0000000000000000
900000003ff00180: 0000000000000000
900000003ff00188: 0000000000000000
900000003ff00190: 00000000000000f0
900000003ff00198: 0000000000000000
900000003ff001a0: 00000000000000f0
900000003ff001a8: 00000000000000f1
900000003ff001b0: 00000000800000f0
900000003ff001b8: 0000000000000000

======read HT config reg:
90000efdfb000000: 0000000000000000
90000efdfb000060: 0080fff0c0000000
90000efdfb000068: 00008000c0000000
90000efdfb000070: 0000000000000000

 spd_info_store begain.

 spd_info_store done.
Copy PMON to execute location...
  start = 0x8f900000
  s0 = 0x30300000
  _edata = 0x8f991010
  _end = 0x8f992028copy text section done.
Copy PMON to execute location done.
sp=8f8fc000
Uncompressing Bios......................................................................OK,Booting Bios
memorysize_high: 0x1f0000000
FREQ
RTC: 18-09-26 18:18:54
FREI
cpu fre 799980000
DONE
DEVI
init uhci cmd called
ENVI
MAPV
in envinit
nvram=bfc00000
NVRAM@bfc09000
STDV
80100000:  memory between 8f7ff400-8f800000  is already been allocated,heap is already above this point
SBDD
rs780_early_setup
enter rs780_por_pcicfg_init
exit rs780_por_pcicfg_init
enter rs780_por_mc_index_init
exit rs780_por_mc_index_init
enter rs780_por_misc_index_init
exit rs780_por_misc_index_init
enter rs780_por_htiu_index_init
before lower tom2 is 0, upper tom2 0
lower tom2 is 1, upper tom2 80
exit rs780_por_htiu_index_init
sb700_early_setup
set a-link bridge access address
To enable ab bif dam access
Enabling Non-Posted Memory Write for the K8 Platform
set smbus iobase
enable smbus controller interface
KB2RstEnable
Enable ISA address decoding
Enable ISA address 0xc0000-0xdffff decode
Enable decode cycles to IO controls
Disabling Legacy USB Fast SMI
Features Enable
SerialIrq Control
IO Address Enable
set ide as primary
Set smbus iospace enable
IO Address Enable
sb700_devices_por_init(): IDE Device, BDF:0-20-1
Disable prefetch
sb700_devices_por_init(): LPC Device, BDF:0-20-3
DMA enable
IO Port Decode Enable
IO/Mem Port Decode Enable
Enable Tpm12_en and Tpm_legacy
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
Arbiter enable
CIM set this register
enable pcib_dual_en_up
sb700_devices_por_init(): SATA Device, BDF:0-17-0
PHY Global Control
sb700_pmio_por_init()
Enabling Spread Spectrum
rs780_before_pci_fixup
sb700_before_pci_fixup
enable watchdog decode timer
enable IDE explicit prefetch
enabling lpc dma function
disable lpc timeout
disable LPC MSI Capability
disable USB OHCI MSI Capability
disable USB OHCI MSI Capability
rs780_enable
enable_pcie_bar3
config_gpp_core
enter config_gpp_core
get STRAP_BIF_LINK_CONFIG_GPPSB
get STRAP_BIF_LINK_CONFIG_GPP
exit config_gpp_core
rs780_gpp_sb_init
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Power Down Control for Southbridge
set sb payload size:64byte
Program NB PCI table
BTDC: NB_PCI_REG04 = 6.
BTDC: NB_PCI_REG84 = 3000095.
BTDC: NB_PCI_REG4C = 52042.
disable gfx debug
set temporary NB TOM to 0xffffffff
Program NB HTIU table
set NB MISC table
Bus-0, Dev-1, Fun-0.
!!!! uma_memory_top = 8f280000, uma_memory_size = 48000000.
!!!! uma_memory_top = 8f25a8a4, uma_memory_size = 48000000.
Get PCIe configuration space.
original : MMIOBase=10000004
Fixup MMIOBase=40000000
Temporarily disable PCIe configuration space
Set a temporary Bus number.
Set MMIO for AGP target(graphics controller).
Enable memory access
Program Straps
MMIOBase=c0000000
BIF switches into normal functional mode.
NB Revision is A12
Restore APC04, APC18, APC24.
Enable PCIe configuration space.
BTDC: GC is accessible from now on.
Bus-0, Dev-1, Fun-0.
rs780_internal_gfx_enable dev = 0x0x00000800, nb_dev = 0x0x00000000.
Bus-0, Dev-2, Fun-0
rs780_gfx_init, nb_dev=0x0x00000000, dev=0x0x00001000, port=0x2.
misc 28 = 541
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
rs780_gfx_init step2.
device = 2
PcieLinkTraining port=2:lc current state=4000102
Bus-0, Dev-3, Fun-0
rs780_gfx_init, nb_dev=0x0x00000000, dev=0x0x00001800, port=0x3.
rs780_gfx_init step5.9.12.1.
PcieLinkTraining port=3:lc current state=4000102
Bus-0, Dev-4, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Blocks DMA traffic during C3 state
Enabels TLP flushing
check port enable
PcieLinkTraining port=4:lc current state=3050608
PcieTrainPort port=0x4 result=0
Power Down Control for Southbridge
Bus-0, Dev-5, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Blocks DMA traffic during C3 state
Enabels TLP flushing
check port enable
PcieLinkTraining port=5:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=5:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=5:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=5:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=5:lc current state=3050607
PcieTrainPort port=0x5 result=1
Power Down Control for Southbridge
Bus-0, Dev-6, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Blocks DMA traffic during C3 state
Enabels TLP flushing
check port enable
PcieLinkTraining port=6:lc current state=102
PcieTrainPort port=0x6 result=0
Power Down Control for Southbridge
Bus-0, Dev-7, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Blocks DMA traffic during C3 state
Enabels TLP flushing
check port enable
PcieLinkTraining port=7:lc current state=102
PcieTrainPort port=0x7 result=0
Power Down Control for Southbridge
Bus-0, Dev-9, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Blocks DMA traffic during C3 state
Enabels TLP flushing
check port enable
PcieLinkTraining port=9:lc current state=3050608
PcieTrainPort port=0x9 result=0
Power Down Control for Southbridge
Bus-0, Dev-10, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Blocks DMA traffic during C3 state
Enabels TLP flushing
check port enable
PcieLinkTraining port=a:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=a:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=a:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=a:lc current state=2030506
link_width=1, lane_mask=0PcieLinkTraining port=a:lc current state=3050607
PcieTrainPort port=0xa result=1
Power Down Control for Southbridge
Bus-0, Dev-8, Fun-0
init GPP core
Disable slave ordering logic
PCIE initialization
init GPPSB port.
Sets DMA payload size to 64 bytes
Disable RC ordering logic
Ignores DLLs druing L1
Prevents LCto go from L0 to Rcv_L0s if L1 is armed
Sets timer in Config state from 20us to 1us
Turns off offset calibration
Sets number of TX Clocks to drain TX Pipe to 3
empty
LC_BLOCK_EL_IDLE_IN_L0
LC_DONT_GO_TO_L0S_IFL1_ARMED
RXP_REALIGN_ON_EACH_TSX_OR_SKP
Bypass lane de-skew logic if in x1
sets electrical idle threshold
Disable GEN2
Disables GEN2 capability of the device
Disable advertising upconfigure support
STRAP_BIF_DSN_EN
 5.10.8.27-28
Uses the bif_core de-emphasis strength by default
Set TX arbitration algorithm to round robin
check compliance
Power Down Control for Southbridge
clear BAR3 address
Disable writes to the BAR3
sb700_enable
enable_sata
enable usb0
enable usb1
enable usb4
enable usb5
enable usb7
enable lpc
disable bus0 device pcie bridges
disable OHCI and EHCI controller
enable OHCI controller
P12PCIH
PCIH
PCID
---id:ffffffff, pcie-slot device: vendor:ffff product:ffff
 
后来经过跟踪发现跑到 _pci_scan_dev 就不动了,板子是我们自己画的,烧录之前的固件可以进入到系统。我刚接触龙芯平台,好些东西不熟,希望大虾们帮帮我。谢谢
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gugudu

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直接去培训现场问吧,免费的。龙芯中科计划于2018年10月15日至16日在北京举办免费技术培训。华北宾馆(北京市石景山区八大处甲1号)
2018-09-27_21-38-03_创建的截图.png

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